The increasing demand for portable products is driving semiconductor device design to place a premium on package size and density (smaller, thinner, cheaper, and with higher functionality per unit volume). Packaging has become one of the most critical enabling technologies for future integrated circuit (IC) generations due to the perpetually increasing needs for higher electrical performance, increased densities, and miniaturization. Addressing the size and efficiency of packaging devices, two technology enablers have been introduced over the last five years: Chip scale packaging (“CSP”) including ball grid array (“BGA”) and Flip Chip (“bumped”), and Wafer level packaging (“WLP”). However, typical wafer thinning technologies cannot be used to achieve the preferred finished part thickness without damage.
With other components of the final package already thinned as much as possible, further reductions in package thickness require thinning of the die itself. Manufacturers need wafer thinning technology that can enable the wafer level packaging (“WLP”) and flip chip packaging utilizing bump to meet ultra thin packaged part demands for portable, wireless and memory intensive applications. As consumption continues to increase for miniature IC packages, yield becomes critical. Typical technologies that require significant process steps in multiple tools cannot evolve and typical “workarounds” are a short-term solution.
Typical wafer thinning methods for WLP and flip chip manufacturing utilizing bump suffer from deficiencies in throughput, yield and breakage, damage, automation and integration, number of process steps, and cost of ownership.
Traditional packaging approaches constitute the first category called chip scale packaging (“CSP”) and are characterized by package processes operating on individual, separated die. Typically in CSP processes, the wafer is thinned, diced and placed into a package. Until recently, CSP resulted in packaged parts typically occupying several times the area of the die. Modern CSP BGA and flip chip processes can provide devices at or close to die size. However, as with other CSP processes it is still required to handle discrete die and, in an attempt to improve throughput, discrete die are often “batched” in strips or trays in an attempt to gain some economies of scale.
Wafer level packaging (“WLP”) presents an alternative to CSP and as such constitutes the second major category of packaging. WLP processes are based on the concept of creating the package prior to dicing the wafer. WLP by definition results in packaged parts no larger than the size of the die. In addition the wafer acts as a chip carrier and as such optimizes economies of scale for packaging. WLP offers better electrical performance of the packaged part than most CSP technologies due, in part, to reduced parasitic capacitance. The resulting part is surface mount ready. The costs of the package go down as the wafer size goes up and the packaging process can be done in the back end of line (“BEOL”) portion of a traditional wafer fabrication facility further reducing costs and dependencies to the integrated device manufacturer (“IDM”). As such, WLP could represent significant cost savings over typical technologies.
A shared process component of WLP fabrication with CSP technology is wafer thinning. Industry trends point to reductions in chip thickness of about 5% per year each year since wafer thinning became a requirement. This trend is expected to continue and will contribute significantly to enabling the industry to continue increasing component density. In addition to volume advantages, there are important performance benefits to reducing the thickness of silicon die that can be categorized as both device performance and reliability enhancements including thermal resistance, device reliability, and die stacking. Thinning the die reduces the serial thermal resistance between the active circuitry and the backside of the chip which can be in contact with a heat sink. Thermal resistance is a critical parameter for a variety of chips, such as power and high-speed microprocessors in which overheating can cause failure.
Thickness may also be related to device reliability: Thin die minimize the stress on the device circuitry due to mismatches between the coefficients of thermal expansion (CTE) of materials within the packaged device. Expansion of the different materials in a WLP device and the PCB or flex-circuit on which it is mounted produce opportunities to shear bonds at the interface of the solder ball/bump and the mating pad. Broken or damaged bonds result in failed components.
Thin die may also permit IC stacking for vertical device integration. It is desirable to fit chip stacks inside standard packages, but this requires thin die (i.e., die must be thinned in order to be used in vertical memory stacks). Chip-stack designs are also attractive for the combination of logic/memory, optical/electrical, analog/digital (“mixed signal”) and micro electromechanical systems (MEMS).
There are three conventional methods of wafer thinning: mechanical grinding, chemical-mechanical polishing (CMP), and wet etching. Typically, mechanical grinding thins wafers by pressing a rotating abrasive disk to the backside of a wafer. CMP typically uses a rotating pad with a silica solution. A typical wet etching process uses a liquid phase chemical reaction.
Mechanical grinding is the most commonly used process to thin wafers. However, it induces significant stress and damage to the wafer, which must be removed by subsequent processing. Typically either a wet etch or CMP process is used to reduce the grind-induced stress. The stress may cause the wafer to break or may damage the devices on the wafer. The breakage and damage is a function of the thickness of the wafer relative to its diameter. In typical applications, mechanical grind is limited to the manufacturing of wafers with a finished thickness to diameter ratio of greater than 1 μm/mm. As such, larger wafers could only be ground to greater thickness. For example, a 100 mm diameter wafer could be mechanically ground to 100 μm thick. However, a 300 mm diameter wafer could only be ground to 300 μm. Since manufacturing economies improve with larger thinner wafers, mechanical grinding alone is unacceptable.
In addition, mechanical grinding can cause warping from induced stress. Warping can lead to breakage in subsequent steps and damage to the silicon lattice resulting in degraded device performance. Furthermore, the post grind steps necessary to remove the induced stress decrease throughput, increase process steps, require additional handling of already thinned and possibly warped wafers, and present other difficulties, as well. Finally, ultra thin wafers cannot be created through the mechanical grind process alone.
On the other hand, CMP cannot be used on WLP devices or bumped wafers due to the high pressure placed in the backside of the wafer. Furthermore, CMP has a low throughput. The removal rate is not acceptable for production processing. Although the oldest technique for silicon etching in the industry, wet etching has disadvantages for wafer thinning due to inherent process control difficulties. Also, wet etching requires hazardous chemicals with high disposal costs due to environmental issues. Wet etching has low market penetration of wafer thinning tools due to expense and environmental issues.
Each of these wafer thinning methods add handling steps and expense. Each handling step reduces yield and slows throughput. Moreover, mechanical grind and CMP prevent using solder bump techniques typically incorporated in flip chip and WLP and limit thinning.
As such, many typical wafer thinning technologies are ill-suited for wafer thinning in WLP or flip chip manufacturing. Many other problems and disadvantages of the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention as described herein.